Abstract
In recent years, the technology of multi-level cell (MLC) shows the effectiveness for increasing storage capacity in advanced flash memories. However, using more levels in a cell also reduces the operation margin and increases the bit error rate (BER). Traditional error correction codes (ECC) used for advanced MLC memories face a serious problem caused by high raw- BER. That is, in order to provide higher error-correction performance to keep the reliability of the memory system, more number of parity bits are required. It greatly increases the cost of flash memories to store the large number of parity bits. Hence, a lot of research articles focus on new ECC schemes for improving the reliability of next generation of MLC memories. Low-density parity-check (LDPC) codes, which have been widely adopted in communication applications, are gaining more and more attention as the superior error correction ability. To improve the reliability for advanced multilevel flash memories, this thesis proposes a methodology to construct an LDPC ECC scheme for advanced flash memories. The contribution includes (1) the simulation model of MLC flash for different raw-BERs; (2) the novel non-uniformly read voltages scheme to estimate the soft information; (3) paritycheck and generator matrix construction and error correction performance evaluation, and (4) hardware architecture design for the trade-off between area and latency. The experiment results show that the codeword error rate (CER) of the proposed (9180, 8364, 816) LDPC ECC scheme is 10^6 times smaller than that of the (9178, 8352, 59) BCH code using 826 parity bits when the raw-BER is 6.0E-03 in a 2-bit/cell MLC memory. The encoder/decoder area of the proposed LDPC CODEC is 42.89K/313.48K gate, and the encoding/decoding latency is 10.66/16.32 μs, respectively. The area cost of the proposed LDPC CODEC is comparable with that of BCH CODEC with the same number of parity bits. Moveover, the encoding and decoding latency meets the throughput requirement of the Open NAND Flash Interface (ONFI) specification. It shows that the proposed LDPC CODEC constructed by our flow is an effective error correction alternative for coping with the urgent reliability issue of advanced flash memories. Our methodology can be applied once given the target flash model of design specification and error distribution. Our future work includes, the evaluation of the new parity-check matrix for improving the error correction performance, the construction of the hardware emulation environment for further analysis (e.g., error floor and error correction performance of new parity-check matrix).