Abstract
With the evolution of technology, Moore's Law will go to the limit in recent years. Three-dimensional stack is a good method of the continuation of Moore's Law. The development of three-dimensional process is the most popular topic of research institutions and industry, three-dimensional stack integration can reduce the circuit size and the transmission loss in the circuit board. There are still many problems to be solved and 3D integration is the hottest topic to solve these problems and provide outstanding performance and high density at the same time. But there are many issues surfaced such as the heavy loading of TSV, large TSV pitch and power issue in Wide I/O. Therefore, how to improve the transfer performance and provide efficiency circuit architectures has been an important issue. In the thesis, we proposed the Charge-Sharing Transfer Scheme to reduce the power consumption of TSV and our circuit does not need pre-charge in every cycle time. We use small swing sensing for reducing large capacitor loading effect. Our circuit can overcome the large power consumption in wide I/O issue. And we proposed the Semi-Master Slave scheme to solve the stacking conditions such like yield, at-speed testing, and die-to-die variation. By our tracking scheme, we can stack our IC in multi-numbers of stacking. A 64kb 2 layer 3D-SRAM macro has been fabricated in 90nm bulk CMOS technology to verify the idea of this work. Our circuit has 82% access time improved and 32% power reduction, compare to single end transfer scheme.