Abstract
ULTRA WIDE BAND(UWB) communication systems, which enable one to deliver data from a rate of 110 Mb/s at a distance of 10 m to a rate of 480 Mb/s at a distance of 2 m in realistic multipath environment while consuming very little power and silicon area, are currently the focus of research and development of wireless personal area networks(WPANs). The data sampling rate from the analog-to-digital converter to the physicallayer is up to 528 Msample/s or more, it is a challenge to realize the physical layer of the UWB system, especially the components with high computational complexity－FFT/IFFT. This thesis deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by radix-2(3) and proposed radix-2(4) algorithm and we applied this design in Single-Delay-Feedback(SDF) architecture.