Abstract
Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices. Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.