Abstract
The raising complexity of system architectures makes it more difficult to exploit the design space. For design space exploitation, trace-driven simulation is becoming indispensable due to its simplicity and speed. Unfortunately, the timing produced by trace-driven simulation is often inaccurate by a large margin. This is because the event timing in traditional trace-driven simulators is fixed and cannot be adjusted dynamically according to results out of the simulators. Dependency-aware simulators solve the accuracy problem, but they require close interactions between the input traces and the simulators. Many traditional simulators process trace events in batch, which require non-negligible modification efforts to make them interactive. This thesis solves the problem by adopting an iterative strategy. There is no need to modify the simulators, except perhaps in reading and reformatting the input traces. Our evaluations using Gem5 and BookSim for Network-on-Chip (NoC) simulation show that this technique can achieve up to 28.75% improvement in timing accuracy compared to the traditional trace-driven simulators, and result in only 3.73% error in average in terms of network latency compared to full-system simulators.