Modeling and Analysis for Parametric Yield Enhancement in Semiconductor Manufacturing and an Empirical Study

Thesis

Lee, Peng Chieh

Masters, 國立清華大學, 工業工程與工程管理學系

2016

Abstract

資料挖礦

半導體製造

晶圓允收測試

電性參數

高共線性

偏最小平方法

約束型偏最小平方法

Data Mining

Semiconductor Manufacturing

Wafer Acceptance Test

Electrical parameters

High collinearity

Partial Least Square

Constrained Partial Least Square

因申請專利緣故，資料延後公開

1 Record Views

Title: Modeling and Analysis for Parametric Yield Enhancement in Semiconductor Manufacturing and an Empirical Study
Translated title: Modeling and Analysis for Parametric Yield Enhancement in Semiconductor Manufacturing and an Empirical Study
Creators: Lee, Peng Chieh
Contributors: Chien, Chen Fu (Advisor)
Awarding Institution: 國立清華大學, 工業工程與工程管理學系; Masters
Theses and Dissertations: Masters, 國立清華大學, 工業工程與工程管理學系
Language: English
Resource Type: Thesis
Date published: 2017