Abstract
As the VLSI manufacturing technology advances into the deep sub-micron (DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which puts different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M), or 1 poly with 5 metal layers (1P5M). Dies with different desired manufacturing processes cannot be produced from the same wafer, but they can be put onto the same set of masks in order to reduce the total cost of used masks and wafers. In this thesis, we propose a novel integer linear programming (ILP)-based floorplanner for shuttle runs consisting of projects requiring different desired processes. A simulated annealing-based side-to-side wafer dicing planner which takes into account the circular shape of the wafer is also presented. This problem formulation was not considered and discussed before. Experimental results show that our approach achieves 28% wafer reduction on average compared to a previous simulated annealing-based reticle floorplanner.