Abstract
本文主要在研究以新的方法形成金屬矽化淺接面，並將之應用極大型積體 電路 (ULSI)。實驗的方向乃將金氧半場效電晶體 (MOSFET) 之 (1)源極 與汲極 (Source and Drain) 淺接面與(2) 閘極上之矽化物分別研究。在 源極與汲極淺接面方面，實驗探討了金屬與離子植入過之複晶矽(ITP)、 非晶矽(ITA)、層狀非晶矽 (ITSA)，其產生之金屬矽化物的高溫熱穩定性 。在此實驗中，我們發現對矽化鎳而言，複晶矽試片的片電阻於 900℃ 即惡化，但對 25keV佈植的非晶矽試片，其片電阻在 900℃ 退火並未惡 化，而對層狀非晶矽試片而言，25keV與 70keV 佈植的試片在 900℃ 退 火後，仍能保持低的片電阻。而矽化鈷與矽化鈦其三種結構的試片皆能 在 100℃或 950℃ 退火溫度之下保有低的片電阻值。另外，實驗亦觀察 了矽化鎳、矽化鈷以及矽化鈦在 0.6micrometer到 2micrometer面積中的 形成。並發現在 0.6micrometer 寬的長溝中，矽化鎳會著溫度的上升 至800℃而聚集成球狀，而矽化鈷並無此聚集現象。另外，矽化鈦在 750℃因 C49-C54的相變化，矽化鈦與矽晶片的接面比 850℃、 950℃ 之 接面還不平整。實驗並探討了用快速退火法與以離子植入鎳金屬或矽化鎳 的方法而形成淺接面的可能。結果發現硼離子無法在如此短時間內分佈成 淺接面並導致漏電很大。在閘極實驗方面，我們探討了閘極與源極/汲極 之間的間隙氧化層(Spacer)在形成矽化鎳淺接面的過程中是否會與鎳反應 而導致此絕緣層的橋式效應(Bridging Effect)漏電，由此實驗得到較高 的第一次退火溫度會導致較不平整的矽化物表面，且 Ar 氣氛在 500℃ 以下會導致較平之表面，但超過 550℃時，N2 氣氛退火會導致較平表面 。 This thesis investigated novel techniques to form the silicided shallow junctions for the application in ultra-large- scale-integrated (ULSI) circuits. The experiments divided the contents into two parts for the MOSFET applications. One part is for the silicided shallow junctions of source and drain, and the other is for the silicides sidewall spacer oxide of gate. The discussion of source/drain applications included the thermal stability of metal silicides on ion implanted polysilicon (ITP), ion implanted amorphous silicon, and ion implanted stacked amorphous silicon (ITSA). For nickel silicide, the sheet resistance values of ITP samples got worse at 900 ℃, but for 25keV implanted ITA sample, the sheet resistance value didn't get worse at 900℃ annealing. For ITSA samples, both of 25keV and 70keV- implanted sample annealed at 900℃ could keep the sheet resistance as low as at 800℃ annealed. However, for cobalt silicide and titanium silicide, all of the three kinds of silicon structure could keep low sheet resistance after 1000℃ and 950℃ annealed, respectively. In the experiments we also inspected the silicide formation in small size windows. Nickel silicide tended to agglomerate as the annealing temperature rose, however, cobalt silicide didn't have this phenomenon. But for titanium silicide, because there was a C49 to C54 phase transformation at 750℃, the silicide/ silicon interface for 750℃ annealed samples were more rough than the 850℃ and 950℃ annealed samples. For gate application, we discussed the bridging effect of sidewall spacer oxide and find the lower annealing temperature leaded to smoother silicide surface. And annealing in Ar ambient could lead to more smooth surface below 500℃ but annealing in N2 ambient leaded to more smooth surface at 550℃.