Abstract
Since the performance of a circuit is always a key factor to be considered, timing analysis, whose result guides timing optimization, is the most important procedure in the design flow. Timing analysis is the step to evaluates the timing behavior of a circuit and checks whether the design can meet timing constraints or not. Current industrial EDA tools still use Static Timing Analysis (STA) as the mainstream. Due to its importance in the design flow, we need to carefully consider various factors so as to have better efficiency. In this thesis, we study two important issues in STA: true path determination and timing constraint verification. We propose an effective algorithm for the true path determination problem and share the experiences of designing an efficient STA engine to verify that all timing constraints of a circuit are satisfied. Experimental results show the efficiency of the proposed algorithm and we also find some interesting trends in the results.