Abstract
Since the implementation of true 3D ICs is still problematic, interposer-based 3D ICs (or known as 2.5D ICs) has been seen as an alternative approach. In a 2.5D IC, the floorplan of dies on the interposer and the signal assignment of macro-bumps and TSVs would impact the routing wirelength, and therefore die floorplanning and signal assignment are critical problems for 2.5D ICs. In this thesis, we focus on reducing wirelength and consider all the interconnects from the chip level to the package and PCB levels. We perform our optimization flow that iteratively performs incremental floorplanning to adjust the positions of dies on the interposer by a linear-programming algorithm and signal reassignment for micro-bumps and TSVs by a min-cost max-flow algorithm until no more improvement on wirelength. The experimental results show that the proposed flow indeed help further reduce the total wirelength.;.