Abstract
As process nodes continue to shrink, self-aligned double pattern (SADP) has become one of the most promising techniques for advanced lithography. Existing works for SADP focus more on layout decomposition and routing, while very few attempts are on placement. However, modifying SADP unfriendly patterns in a final layout requires high efforts, so how to generate an SADP friendly layout in an early physical design stage such as placement becomes important. In this thesis, we study the problem of refining a standard cell placement for SADP, which asks to simultaneously refine a detailed placement and find a valid SADP layout decomposition such that both overlay violation and wirelength are as small as possible. Based on the techniques of white space insertion and cell flipping, we propose an approach to the addressed placement refinement problem. Experimental results show the efficacy of our approach