Abstract
Abstract As the semiconductor technology advances, the interconnect line width and spacing shrink. The parasitic resistance and capacitance, as a result, increase. In turn, the increases in resistance and capacitance increases interconnect delay, IR drop and crosstalk. All these impact on chip performance. Furthermore, the reduction in line space increases the electric field in the dielectric between metal lines. Thus, time dependent dielectric breakdown (TDDB) needs to be investigated and resolved before the technology is fully qualified. Before the dielectric is completely breakdown (hard breakdown), leakage current has been observed to increase (soft breakdown). It has been theorized that in Cu/LK interconnect technology, Cu ion can be out-diffused into the dielectric, thus increases the leakage current. During this time, the interconnect capacitance might have been changed. Due to lack of a good real time monitor circuit, we do not know how does the interconnect capacitance change during this time. A real-time capacitance monitor test circuit is developed in this thesis. It is implemented using TSMC 65LP technology. The target capacitance is 20fF. But, the circuit can be easily ported to other (more advanced) technology easily, since it consists of mostly simple inverters. The sensitivity to the monitored capacitance is further increased by using Miller Effect. The signals on the two terminals of the capacitor is completely out of phase, thus magnifies the capacitance. Assuming a 5% change in monitored capacitance, 5.9% to 6.7% changes in frequency have been observed in simulations. On the other hand, instead of measure frequency, we also can measure current or power by connecting buffer chain to obtain the capacitance changing.