Abstract
Optical communication has played an important role in wide area networks (WAN) and local area networks (LAN). The trend motivates on low-cost low-power fully integrated transceiver. The transceiver integrates both transmitter and receiver function into a single chip. Here the receiver is focused on. A critical task in such receivers is post-amplifier that enlarges the amplitude-varying signal into the saturation level and provides stable signal for the clock and data recovery circuits (CDR). For the sake of achieving cost-down of optical transceiver, this thesis proposes a 1.25Gbps post-amplifier by using 0.35μm CMOS technology. This thesis presents a new loss-of-signal function with programmable input-signal level detection to maintain bit-error-rate (BER) performance. Furthermore, the method of gain stages optimization is addressed in this thesis. In this work, the proposed post-amplifier employs novel gain cells to achieve an input sensitivity 4mVp-p, 47dB conversion gain and 1.52GHz bandwidth operating at 3.3V. And the simulated electrical characteristics achieve or meet the specifications of IEEE 802.3z (Gigabit Ethernet).