Abstract
An algorithm is proposed to design high fault-coverage LFSRs and reseeding logic as a test pattern generator of a transition-fault BIST. First, we develop a simulated annealing (SA) algorithm to search a high-quality LFSR and then using our proposed reseeding method to increase the fault coverage. In our SA process, there are many times to estimate LFSRs. So we develop a process incorporating a probability-based estimator and a fast fault simulation in simulated annealing framework. Therefore, we can select fastly one high-quality LFSR for detecting the transition faults of a circuit. For the remaining hard-to-detect faults, test patterns are generated with a specialized ATPG model. Another search process is then invoked to select high fault-coverage seeds for the LFSR from test patterns. The constructed hardware LFSR generator can increase the pseudo-random fault coverage as much as 3.26% without any additional overheads. Also the selected seeds can generate the same deterministic fault coverage with only 1.1% of the original test patterns.