Abstract
In this thesis, we present an output-pattern directed circuit decomposition to reduce power consumption. We observed that in some circuits, highly active output-pattern falls into only a few patterns.Based on this observation, we propose a decomposition architecture and an algorithm to synthesize the decomposed logic. In the decomposed architecture, one small part is used to compute a few highly occurred output-patterns, and the other large part is used for all the other infrequently occurred output-patterns. Consequently, most of time, only the small part of the circuit is active so as to reduce power consumption. In addition, we propose to use an OBDD-based heuristic algorithm to compute the output-pattern frequency in a very short CPU time. Several MCNC benchmark circuits were tested to show the performance. The results shows that the proposed method can achieve 64.9% reduction in power with little area increase as compared to circuits without decomposition.