Abstract
Since packages affect the amount of heat transfer, it is important to include package and heat sink in thermal analysis. In the first work of this thesis, we study the full-chip thermal response with different packages. We first discuss the difficulties of obtaining accurate package models for simulation. To facilitate a designer to perform thermal simulation with different packages, we propose to use a matrix called the package-transfer matrix (PT-matrix), which can transform a temperature profile of one package to another temperature profile of the desired package. To estimate and verify a PT-matrix, we propose an efficient method which uses infrared radiation images from two carefully design test chips with PBGA packages. Furthermore, thermal and thermal-induced mechanical problems in 3D or 2.5D stacking-die technologies using through-silicon-via (TSV) technology are known to be more severe than those in 2D circuits. Many researchers have proposed efficient design for TSV reliability to alleviate the hot spot problem and to reduce the wire-length. However, in addition to the thermal and wire-length issues, we show that TSV reliability can be enhanced by reducing the die fracture. In the second work of the thesis, we propose a novel design methodology based on Gur Game for stacking-IC reliability simultaneously considering die fracture, temperature, and wire-length constraints.