Abstract
NAND Flash memory plays an important role to data storage in the modern semiconductor memory. With the smallest cell area in the planar semiconductor memory, NAND Flash memory can achieve high cell density and low cost. Conventional large capacity data storage media is hard disk driver. It needs to use the dynamic mechanical structure to rotate the magnetic disc to read and write data. This characteristic makes it hard to be used in the portable device and have the disadvantage of high power and low throughput. Recently, the NAND Flash memory is widely used in the portable electronic products such as smartphone and tablet and high performance data storage media such as Solid State Disk (SSD). The state of art of the modern NAND Flash technology has reaching 1x nanometer node. The technology scaling has become more and more difficult and expensive. In the near future, the technology shrinking will not be the effective method to reduce the cost. In order to achieve high storage capacity, the three dimensional NAND Flash technology is regarded as the solution of the next generation large data storage application in the recent year. The random access speed of NAND Flash memory is quite slow. To achieve high data throughput, NAND Flash memory uses large page size and simultaneous sensing. Every one or two bit lines are connected to one sensing circuit called page buffer. It needs to sense the several tens nano ampere cell current and support the program and erase verify scheme. We proposed a page buffer circuit for 75nm 3DVG BE-SONOS NAND Flash memory. It can support layer aware verify to compensate the different threshold voltage requirement for different layer in the 3DVG structure. It uses the reverse sensing scheme to eliminate the source line noise and supports the multi-sensing scheme to reduce the BL coupling noise.