Abstract
Data dimensionality reduction techniques let people understand the structure of the multi-dimensional data. Data mining, pattern recognition or machine learning take it to analyze data and retrieve the implicit information from data in the high dimensional space. A lot of algorithms have proposed to process the linear data or non-linear data dimensionality reduction. In this thesis, we try to propose the parallel data dimensionality reduction formulations and implement them on the Chip of the Multi-core Processor (CMP). Multi-core microprocessor has been the main stream in the computer. Graphic Processing Unit (GPU) is emerging as the many core architecture with the multi-thread programming platform. The new generation GPU with powerful computing capacities that is not only suitable for dealing with graphic processing but also solving the problems in various applications. Most of data dimensionality reduction techniques take the nearest neighbor (NN) graph construction or take the all pairs shortest paths (APSP) algorithm to approximate data. We conduct these two methods in parallel on the GPU. We can speed up NN about 10X and APSP algorithm about 2X. At last, we upgrade 20% to 50% manifold learning computation performance.