Abstract
3D Integration that includes many dies on a single packaging substrate has been touted as a new trend for future integrated circuits. In addition to System-in-Package (SiP) and TSV-based stacked IC, the interposer-based 3D IC has been recently proposed by companies like TSMC as another cost-effective alternative. With many advantages like lower cost, ease-of-manufacturing, higher yield, etc., it could become an attractive solution for many portable devices that requires lower power, heterogeneous components, and small and thin form factor. However, to make such an interposer-based 3D IC feasible and reliable, numerous challenging issues on design, testing, and diagnosis remain to be resolved. This thesis addresses the testing and characterization of interposer wires in a 2.5-D stacked IC, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First of all, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults) but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Secondly, our method can also be used to characterize the propagation delay across each fault-free interposer wire.