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Path Delay Fault Collapsing by Linear Structures of Critical Paths
Thesis

Path Delay Fault Collapsing by Linear Structures of Critical Paths

Pei-Ying Hsieh
Masters, 國立清華大學, 電機工程學系
2005

Abstract

延遲測試 延遲錯誤 路徑延遲錯誤模型 線性組合 功能敏化性路徑
Paths in a circuit are structurally related to each other. Therefore, under certain assumptions, an unknown path delay could be calculated as a linear combination of known path delays [1]. In other words the delays of all paths of a circuit could be showed as a linear combination of the delays of a small subset of paths called the basis path set [2]. To find the maximum path delay, it must know the delay of all paths, either by direct measurement or by calculation. This means that every path not directly measured by a test pattern must be equal to a linear combination of basis path set. In this thesis, we improve the algorithm of determining linearly dependent paths based on the one given [2]. We combine some same and redundant structures of a circuit graph and increase more testable paths to the basis path set. Then, we will get more linearly dependent paths. The experimental results for benchmark circuits are given.

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