Abstract
In this thesis, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation ring test, in which two TSVs are connected with some peripheral circuits to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring - a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. In addition to two TSVs to be characterized, we also present lots of TSVs characterization scheme to avoid the synchronous issue. Monte-Carlo analysis of a typical TSV with 30% width variation of transistors and routing wires variation occurring shows that characterization error of this method is average within 2% and the prediction of the capacitances of TSVs within 8%.