Abstract
We consider the problem of circuit clustering for hierarchical FPGA architecture. One motivation for studying this problem is the current need of good clustering tools for implementing a circuit on hierarchical FPGA architecture. In this paper, we present an efficient performance-driven circuit clustering algorithm subject to area and pin constraints on each level under specific delay model. Experiment results show that our algorithm can improve the circuit performance by 5.5% as compared to another performance-driven clustering tool [8] and 16.2% to area-driven clustering tool [9].