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Performance improvement of LDPC coded systems by dynamic scheduling and selective mapping
Thesis

Performance improvement of LDPC coded systems by dynamic scheduling and selective mapping

Lin, Chi-Yu
Masters, 國立清華大學, 電機工程學系
2008

Abstract

動態排程 低密度奇偶檢查碼 LDPC dynamic scheduling
In this thesis, we propose a dynamic scheduling decoding method, to accelerate the decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes used in the IEEE 802.16e standards based on a previously proposed decoding architecture. We dynamically skip, redo or do other decoding operations for each layered based on appropriate criteria. An early termination strategy which is efficient in hardware implementation is also proposed in this thesis. The modified message-passing decoding (MPD) using these two techniques simultaneously can reduce the computational complexity with similar error performance as compared to the case of not using these two techniques.

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