Abstract
A mutlicore simulator is useful on multicore programming, which gives programmers an insight into the internal states of multicore systems. Due to the growing number of processors, complicated interconnections, and the frequent data communications of running threads, the simulation process of a multicore application increasingly costs a significant amount of time. In addition, the bug detecting process for multi-core platforms tends to be more difficult and the debugging process might iterate for many times and thus consumes more simulation time. In this thesis, we propose two kinds of components to help programmers who needs to debug their applications on such a multicore platform. First, we propose a trace component which can be integrated into processors, memory, and other components on the simulation platform. This component keeps track of the operations of multicore simulation environment and provides enough information for analyzing the problems or even re-entering a continuation point of a simulation for debugging purposes. The other component we proposed is an assertion component. With the assertion component, we can check the behavior of an application with the golden models provided by programmers. The assertion component can indicate the point where the application just went wrong according to the provided model. These capabilities help us finding out the problems caused by the interaction between components which are hard to be detected by conventional debugging tools. In addition, assertion component presents a trace-on-demand methodology such that the simulation performance, the trace data size, and the recovering time can have a good compromise. Besides, an analytical model for possible trace data size is also given to assist programmers in making trace decisions. The experimental results in different views of trace information by incorporating our proposed approach in a multicore DSP simulator reveal that our analytical model for estimating log size is with accuracy with predicting errors less than 6%.