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Post-Placement Timing Improvement by Flip-Flop Swapping
Thesis

Post-Placement Timing Improvement by Flip-Flop Swapping

Jung, Shih Yuan
Masters, 國立清華大學, 資訊工程學系
2014

Abstract

時序驅動佈局 可用時序差異 正反器 電子設計自動化 Timing-Driven Placement Useful Skew Flip-Flop EDA
Timing-driven placement is a well-known technique that relocates cells along critical paths to improve timing. Traditional approaches fix timing violation while treating clock skew as given. We propose a flip-flop swapping algorithm for adding useful skew. We derive a gain function reflecting timing slack variation from flip-flop swapping. By employing a hybrid of net-based and path-based structure, it facilitates trade off between timing accuracy and time complexity. We test our approach with the benchmark contents of top three winners of ICCAD 2014 contest. Experiment results show our placer achieves better timing improvement than their solutions.

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