Abstract
Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its gains in coding and diversity. However, its great decoding complexity makes it less promising in chip realization compared to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm. Compared with the Viterbi decoder for convolutional code, the STTC Viterbi decoder has a large amount of the complex-number multiplications to calculate the branch metrics. Besides, the amount of the branch metric calculations increases significantly in proportional with the number of antennas and the modulation order. The large amount of calculation and complexity design is a major result that STTC code is not applied to the specifications of wireless communication systems. In order to overcome the bottleneck, we propose an algorithm which reduce the complexity of the Viterbi decoder for STTC. The proposed Viterbi decoder for STTC apply the well-known algorithm, T-algorithm, to reduce the calculations of branch metric and reduce the complexity of the hardware design. Beside, the proposed Viterbi decoder uses the characteristics of the STTC code and hardware architecture to provide accuracy estimated SNR value. The proposed Viterbi decoder reduces the complexity and the power consumption in proportional to the SNR value. Based on the proposed Viterbi decoder, a reconfigurable MIMO STTC Viterbi decoder is designed and implemented using 0.18 um technology. The proposed decoder supports the QPSK, 8PSK and 16-QAM modulations with 4×1 and 4×4 MIMO system. The throughput of the proposed decoder achieves 59.2Mbps, 33.8Mbps, and 15.0Mbps for Q-PSK, 8-PSK, and 16-QAM modulations, respectively.