Abstract
High-level power estimation often relies on different power models. The modeling procedure of IPs is usually complex and time-consuming. In this thesis, we use quick and effective methodologies to model various IPs. We have two modeling strategies for different IPs. Firstly, we use some key signals to classify the operation modes of IPs and create the power model, called General IP model. Secondly, we adopt the instruction-level and stage-accurate approaches to characterize processor energy model that is based on the realistic instruction type and program counter registers to establish an accurate model. The proposed methodology is applied on AES and PAC-DSP core to create versatile power models for performing the gate-level power estimation. The realistic application programs are used as training patterns due to its similarity to operating environment, and thus, the overhead of generating specific training patterns for each IPs is ignored. With general IP model, the estimate error of processor is about 10%, and the error could be reduced to only 2.43% by the stage-accurate model. Moreover, the speedup of our approach is 780X faster than gate-level simulation.