Abstract
This thesis presents a new timing-tracking scheme in an SRAM design for enhancing the tolerance capability of bitline variation. This scheme, modifying the circuitry around each sense amplifier, allows an SRAM column to operate according its own timing. Thus, each latch-based sense amplifier can be turned on at the right time and the pulse width of the active wordline can be tuned to its optimal width on the fly, no matter how severe the operation speed of a bitline differs from the other. Pre-layout SPICE simulation with 1K-bit SRAM cells demonstrates the effectiveness of this scheme. Monte-Carlo simulation with 10% process variation shows that our scheme can improve the yield from 79.2% to 96.3%, as compared to the traditional replica-based timing tracking scheme.