Abstract
In this work, we attempt to give a comprehensive treatment of the problem of utilizing quasi-cyclic low-density parity-check (QC-LDPC) codes efficiently and reliably in NAND flash memory. We start from a theoretical point of view while still take implementation issues into account. To deal with the problem in a concrete manner, a channel model incorporating the major sources of the threshold voltage disturbance in flash memory is proposed from which the log-likelihood ratio (LLR) used in the decoding of LDPC codes is mathematically derived. Based on the LLR and the investigated read techniques, we propose several decoding strategies which constitute an efficient and reliable decoding retry sequence that can be used as a practical solution in actual flash memory. Similar to communication systems, pilot information and the associated scheme are discussed to mitigate performance degradation due to the threshold voltage disturbance in memory cells. Besides decoding strategies, a construction of QC-LDPC codes based on the additive group of a prime field is introduced, and error-floor estimation for the constructed QC-LDPC code is provided as well. Simulation results are presented at the end of this work to verify the effectiveness of the proposed coding scheme and decoding retry sequence.