Abstract
In modern CMOS processes, eight or more interconnect layers are commonplace so that techniques to planarize the surface have become mandatory. Chemical-mechanical polishing (CMP) step is a technique to achieve planarization and dummy metal fills have been widely applied by foundries to VLSI physical layouts for better CMP uniformity and higher manufacturability. As the size getting smaller and smaller, dummy metal fills remain importantly because of dishing and erosion that are caused by CMP. But at the same time, dummy metal fills also cause extra parasitic effects which force the capacitance between interconnects becomes larger. Thus, the impact by dummy metal fills in circuit needs to be modeled accurately and be taken into account in the design flow. It is important to quantify these problems caused by dummy fills and need more researches for better understanding them. In this paper, we will first overview the domain knowledge about dummy metal. Then we will review the related researches in this domain. After that, we’ll present a new and different method (structure) to quantify the impact by dummy metal fills in capacitance, on performance and crosstalk noise. We also analyze the experiment data from our method and make some conclusions. This can help designers to estimate the dummy impact accurately in advance. At last, we also design a software to run the flow automatically. With the software, users can generate the test structures according to their requests (for example: structure length, structure width, structure space and VLSI manufacturing processes) and quantify the parasitic impacts by dummy metal fills in a short time.