Abstract
Memory fault simulator is an important tool for memory test sequence optimization. Traditional sequential fault simulation algorithm has time complexity O(N3) (N: number of cells in memory), which may be too slow to simulate a large number of memory words. Therefore, we had developed a fault simulator called Random Access Memory Simulator for Error Screening (RAMSES). RAMSES uses fault descriptors to describe fault models' behaviors, which can reduce the time complexity to O(N2) and support new fault models. Delay fault plays a more and more important role in memory testing. In this thesis, we adopt new delay fault models targeting DRAM timing parameters and modify RAMSES that is now called RAMSES-D. Finally, the concept of weighted coupling fault is proposed. Fault count itself cannot accurately represent the real coupling fault distribution. Even if the same fault model is concerned, cells in diRerent positions will have diRerent fault occurrence probability. We propose a weight function and assign a weight to each coupling fault, and modify the fault coverage calculation method. The weighted fault coverage shows the effectiveness of the weight function, and that different coupling fault ratio varies with diRerent memory configuraitons. We propose a 23N March test pattern for delay fault models, which reduces 23.3% test length from originally proposed delay fault test patterns. With the weight function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between diRerent memory configurations.