Abstract
With the ever-increasing popularity of electronical communication, data security is becoming a more and more important issue nowadays. In 1976, Diffie and Hellman proposed the concept of public key cryptography which has triggered the revolution of cryptography. In 1978, Rivest, Shamir, and Adleman proposed the RSA public-key cryptosystem based on factoring problem, which has become the most widely used public-key cryptosystem due to the fact that it can be used for both data encryption and authentication. The kernel operation of an RSA public-key cryptosystem is the operation of modular exponentiation, which can be performed by a successoin of modular multiplications. In this thesis, a new bit-serial systolic array for modular multiplication is presented based on a modified Montgomery algorithm. It is highly regular, modular, and thus well suited to be implemented using VLSI techniques. The proposed array can operate at a higher clock rate than the previous array based on the same algortihm due to the fact that the signal-broadcasting problem is avoided in our design. A new VLSI architecture for modular exponentiation, which can be used to fulfill the operation of encryption and decryption of an RSA public-key cryptosystem, is also constructed based on the proposed array for modular multiplication. Comparison results show that the proposed modular exponentiator is rather suitable for those applications where high processing speed is needed. A orototype chip for implementing a 512-bit RSA public-key eryptosystem is designed based on the high-performance COMPASS 0.6μm standard cell library. The gate count of the chip is about 132k and the die size is about 8280μmx8224.8μm. With an estimated clock rate of 166 MHz, a baud rate of 333K bits/second can be achieved.