Abstract
Factoring is a technique of logic minimization to represent a Boolean function in a equivalent function with minimum literals. When realizing the circuit, a function represented in compact form has minimum area. Some Boolean functions even have equivalent forms which each variable appears exactly once in factored functions, which are known as fanout-free functions. John P. Hayes had devised an algorithm to recognize fanout-free functions. We propose a property and some e±cient ways to accelerate this algorithm. With our improvements, execution time of this algorithm are more competitive with other state-of-the-art methods.