Abstract
With the increasingly high complexity and density of modern CMOS circuit, defects caused by parametric and process variations, e.g., are more and more difficult to be detected. The Cell-Aware Test (CAT) methodology has been proposed to generate more realistic input conditions of the cells, which target the cell-internal defects. One can increase the fault coverage by feeding these conditions to the gate-level ATPG. In the first approach of this thesis, we propose an efficient test flow for CAT to drastically reduce the time for CAT-enhanced test generation at the cell level. In the original CAT, the detailed transistor-level circuit simulation is used to find appropriate test patterns, and it has been considered as very time consuming. To solve this problem, first, we exploit the conventional Switch-Level ATPG (SL-ATPG), and experimentally show that it can efficiently generate test patterns in the CAT flow. Second, based on layout-oriented defect generation method, we propose an algorithm to automatically inject those defects into the switching network used in SL-ATPG, for cells in the standard library. Third, note that the traditional ATPG is primarily based on the stuck-at-fault and transition-fault models, it is difficult to find small-delay defects. However, the same defects are likely to be detected by observing the short-circuit current, so we propose current-based checks for a pattern generation method which are able to detect the existence of a short-circuit path. Finally, we compare the simulation time of detailed circuit simulation and that of SL-ATPG in CAT. The experiment is based on a commercial 180nm CMOS standard cell library. The result shows that the SL-ATPG method can successfully reduce the simulation time by about 403X. However, many hard-to-detect defects not located on the critical path can easily escape from all the conventional testing methods including the CAT. The second approach discussed in this thesis is that, in order to further reduce the defect level, we introduce the quorum sensing (QS) methodology to circuit testing (sensing) for improving the quality and reliability. Different from the traditional IDDQ test, burn-in test and stress test, the thermal quorum sensing (TQS) method provoke a thermal chain reaction to expose the subtle variations in the circuit, which can be observed by the common cell population behavior. The experiment is based on a commercial 45nm CMOS standard cell library, and it is verified by the ISCAS s9234 benchmark. The results show that, when the number of small defects injected is more than 489, the difference in total current will be higher than 2.08mA, which can easily be detected. The proposed TQS test methodology combines the stress test, the IDDQ test, and the self-sensing capability by the distributed thermal sensors. Compared with other state-of-the-art or traditional testing methods, quorum sensing can enhance the test quality, providing a new perspective into circuit test.