Abstract
To meet the requirement of low-power consumption, multi-level-cell STT-RAM (MLC STT-RAM) has been widely regarded as a potential candidate for replacing DRAM-based main memory in the next generation computer architectures because of its high cell density, comparable read/write performance and zero refresh power consumption. However, MLC STT-MRAM has higher power consumption than DRAM while a write operation is performed because MLC STT-MRAM sometimes needs to perform a two-step transition to change the original stored bits to another specific written bit patterns. As a result, MLC STT-MRAM has asymmetric power consumption while different bit patterns are written to a memory cell. To the best of our knowledge, a few or none of previous studies consider the feature of asymmetric power consumption to reduce main memory power consumption while STT-RAM is utilizes as a main memory in a computer system. Thus, this study proposes an energy-aware cache replacement policy, namely energy-aware write-back strategy (EWS), which consider asymmetric energy consumption to evict a proper cache block, so as to minimize system energy consumption. The experimental results show that the proposed solution reduces the energy consumption by 23.9% on average, compared with LRU.