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Run-Time Frequency Scaling of On-Chip Networks for GPGPU
Thesis

Run-Time Frequency Scaling of On-Chip Networks for GPGPU

Tu, Chiao-Yun
Masters, 國立清華大學, 資訊工程學系
2012

Abstract

通用圖形處理器 晶片網路 動態頻率調整 GPGPU Network-On-Chip Dynamic Frequency Scaling Many-to-Few-to-Many
Modern General Purpose computing on GPUs (GPGPUs) provide orders of magnitude more computing power than general purpose processors (CPU) for highly parallel applications. Since the traffic pattern of GPGPUs behaves considerably different than CPU, the conventional interconnection network designs for CPU are not applicable for GPGPUs. This thesis proposes a run-time dynamic frequency scaling mechanism that can meet the bandwidth demands of different applications by tuning the frequency of network in response to the network load. In this thesis, we first investigate the characteristics of GPGPU traffic pattern and classify the traffic patterns of GPGPUs to three types. Under the different types, the request network and reply network require different bandwidth to handle the network load. Second, we leverage the property to regulate the network frequency dynamically by monitoring some shader cores and predict the network load. Evaluation show that this dynamic frequency tuning design can achieve up to 27% improvement compared to baseline setting (on average, it results 7.4 % improvement).

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