Abstract
Turbo code can approach the theoretical channel capacity and has been regarded as the standard in the next generation mobile phones. For portable platforms, power consumption is very critical.In this thesis, we focus on the algorithm and VLSI implementation of the low-power SOVA-based Turbo code decoder. SOVA is simpler and more appropriate than MAP for VLSI implementation with a little degradation.A low complexity SOVA (Two-Step SOVA) which precedes VA to find the “almost” final survivor path and then performs the updating operations can reduce the hardware complexity. In order to minimize the state transition for Viterbi decoders, SST (Scarce State Transition) scheme was proposed. It can be easily extended to SOVA decoder. Due to the characteristic of iterative decoding, a termination criterion can be evaluated with a simple additional circuit. Simulation shows 60% iterations can be saved at SNR=3.0dB(if the number of iteration is 6). A low power ACSU (Add-Compare-Select Unit) which saves one adder also lowers the power consumption. We propose two schemes—gated clock and two-phase clock, to further improve the power consumption of the trace-back units.Finally, the design of Turbo code decoder is described with Verilog HDL code and synthesized with Synopsys Design Compiler. The power was estimated with Synopsys Power Compiler. From the simulation, 12.1% power can be saved.