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SRT 除法器的商數函數表之測試設計
Thesis

SRT 除法器的商數函數表之測試設計

張銓淵
Masters, 國立清華大學, 電機工程學系
1998

Abstract

SRT 除法器 P-D 圖 位移餘數 被除數 除數 SRT divider P-D plot Shifted partial remainder dividend divisor
The major problem to be solved here is the testing of the quotient selection table of SRT divider. The quotient selection table is usually implemented using PLA or ROM. The defect of PLA or ROM may cause the misbehavior of only one entry of the quotient selection table. Traditional ways to solve this problem could be random pattern testing or scan methods. However, the fault coverage is relative low for random pattern testing, and the scan methods require extra delays due to the insertions of multiplexers in the critical paths. Therefore, the solution in this thesis is to find the methods that can scan all the entries of the quotient selection table, i.e., 100% coverage, without adding extra delays in normal operation. In this thesis, two methods are proposed to test if the function of the quotient selection table of the SRT divider is correct or not. The first method uses an algorithm to generate a set of dividends to test the quotient selection table. The second method is a BIST design, which used a jump counter as the TPG (Test Pattern Generator). Both methods are focused on testing the folded mode quotient selection table. Therefore, only the partial remainder in the first phase of P-D plot is concerned. The hardware implementations of the dividers are synthesized by CIC 0.6um Compass Cell library. And compare the area overhead of the divider, which designed for the first method or the second method with the original divider. The total testing time for the proposed algorithm is the time for two divisions for radix 2, for 35 divisions for radix 4 and for 360 divisions for radix 8. For 100 MHz processor, the test time is 1.08μs for radix 2, 4.73μs for radix 4 and 64.8μs for radix 8. For proposed BIST structure, the total clock cycles are 18 for radix 2, 210 for radix 4, and 1602 for radix 8. The area overhead for both methods are 5% to 8 %, respectively, compared with the original divider. The major advantage of both methods is no additional component on the critical path. Therefore, there is no delay overhead for both proposed methods.

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