Abstract
To improve the performance of high frequency CMOS integrated circuits for achieving high-speed communication systems, the channel length and gate insulator thickness in MOSFET transistors are continuously scaled down. However, as the dimension keeps reducing, many undesired effects appear such as the increase of leakage current and the low frequency noise. In particular, the low frequency noise (also called flicker noise) becomes an important consideration, since the low frequency noise has a severe impact on the phase noise in RF and mixed-mode circuits, and it also limit the information capacity and detection sensitivity. In this thesis, many basic noise sources in semiconductor devices are reviewed including thermal noise, shot noise, etc. The flicker noise mechanisms and models are discussed in details. Because shallow trench isolation (STI) is the main factor focused in this thesis, STI effect on advanced CMOS characteristics will be discussed, including DC and noise characteristics, from some previous studies and STI properties we will show why we present the symmetric and asymmetric edge-extended layout design. The 0.13μm RF CMOS on chip measurement results are presented. For DC part demonstration, device Vth、Gm and ID which shifted by STI effect all will be included. By symmetric extending the distance between STI edge and the gate channel, the noise value and variation of devices flicker noise were reduced significantly. Under a fixed VDS of 0.7 V and VGS of 0.6 V, the edge extension devices (W/L= 1/0.13, extension distance= 1.2μm) showed a reduced noise current spectral density variation (SID/I2 ranges from 8.45□10-12 to 2.16□10-11 Hz-1 at 100 Hz) to only ~ one percent of that for devices without edge extension (SID/I2 ranges from 2.0□10-10 to 6.12□10-12 Hz-1 at 100 Hz). The noise improvement level depended on the edge extension values was experimentally investigated and measurement results showed that the impact of stress and traps introduced by STI on device flicker noise can be described by the carrier number with correlated mobility model. This study also indicated that the trend of STI effect on NMOS and PMOS noise performance is the same. In addition, when the devices are biased in saturation region the noise characteristics of asymmetric edge extension devices indicated that STI imperfect effect on source side is the main origins to degrade noise performance.