Abstract
In a System-on-Chip (SoC), to fully utilize IPs require system-level optimization. System-level optimization implies minimum modifications on the IPs while boosting the communication efficiency. This paper demonstrates the process and result of a system-level analysis and optimization on an H.264/AVC video decoder SoC. Four optimization approaches, including two that minimize DRAM access penalty and two that minimize system idle time, together reduce total execution cycles (i.e. total bus cycles) by up to 12.3%, increase DRAM row-hits on bus-grant handover by up to 242%, and decrease system idle cycles by up to 84% on decoding B frames. This paper also adopts the Warning-line Based Algorithm (WBA) to support Real-Time (RT) bus masters. All proposed methodologies, techniques, IP designs, as well as reasoning involved in optimizing this video decoder intend to be applicable also on other bus-enabled SoCs.