Abstract
One of the most e®ective way to achieve low power is using multiple supply votages and multiple threshold voltages with gate sizing for modern ASIC designs. We propose a sensitivity based approach to minimize the total power consumption using simultaneous Vdd and Vth voltage assignment with gate sizing that take the level shifters into consideration. The experimental results show that our algorithm can obtain 36.3% and 35.2% average total power savings for nominal primary input activity and low primary input activity, respectively. Compared with a two stage Vdd and Vth voltage assignment with gate sizing algorithm in [13], our algorithm also consume 4.2% and 9.7% less average total power than it. Finally, since we perform Vdd and Vth assignment simultaneously, it makes the total runtime very long. So we propose a static adjustment and a dynamic adjustment approaches to reduce the total runtime of our algorithm.