Abstract
Self-aligned double patterning (SADP) has become one of the most promising lithography techniques for advanced technology nodes. In SADP, overlay violation is a critical issue for fabrication, and therefore the minimization of overlay violation is getting more important. Most of existing SADP-aware physical design works focus on layout decomposition and routing, while only very few attempts are for placement. But if we can generate an SADP friendly layout in the placement stage, the subsequent layout modification efforts will be much more reduced. In this thesis, we study the following SADP-aware problems: (1) single row cell-based detailed placement with variable row width, and (2) single row cell-based detailed placement with fixed row width. In both problems, overlay violation can be reduced by two cell placement techniques: white space insertion and cell flipping. For each problem, we develop two placement algorithms. The first one adopts only the white space insertion technique, and the second one adopts both white space insertion and cell flipping techniques. Experimental results show that our methods can effectively reduce overlay violation.