Abstract
In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this thesis, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 92% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) [8] are 231%, 265%, and 276%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [8] in reducing peak current and power/ground noises.