Abstract
Jitter measurement is an important issue of PLL BIST (Build-In-Self-Test), and the accuracy of jitter measurement is dependent on deadzone of DFFs, which is the summation of setup time and hold time. This thesis developed DFFs based on TSPC (True Single Phase Clock) technique. The proposed DFFs includes Set/Reset function in order to allow preset initial values for digital design, and feedback structures were added to improve low frequency operation which is a weakness of dynamic DFF structure. To verify the on-chip performance of these proposed DFFs and to compare with standard cell library DFFs, a test circuit based on under-sampling method had been designed, and a test board had also been designed and implemented for the accurate on-chip measurement. The simulation results, obtained from a 0.13 um technology, show about 60% deadzone and 55% intrinsic delay improvements over the standard cell library DFFs. The test circuit is partial work during on-chip measurement because there has some incorrect design in test circuit and the noises of clock signals are much larger than SPEC which decreasing the resolution and causing the failed results. For ultra-low power applications, sub-threshold region operation is preferred. This thesis analyzes different types of DFF with proposed DFFs to compare deadzone, delay with DC analysis which could provide a steady state simulation and a transient analysis which could simulate the actually performance. Thus recommendations on DFF structures in different application will be developed. Due to operating theory of MOSFETs are different between subthreshold region and normal region, an optimal method which could find an optimal size of proposed DFFs is also mentioned. And the performance of optimal proposed DFFs have a huge improvement of deadzone with standard DFFs which is about 90% in average when supply voltage sweep from 0.20V to 0.30V.