Abstract
A fully standard cell-based all-digital phase-locked loop (ADPLL) with wide tracking range of frequency is presented. The three-gear digitally controlled oscillator (3G-DCO) designed in this work adopts three different control methods (including path-selection, driving-strength controlling, and loading capacitance controlling) and a novel configuration to achieve the goal of improving not only the maximum output frequency, but also the output frequency range and the resolution of the DCO simultaneously. Combined with a proposed Mirror-DCO-Based Calibration Mechanism and a Smart Code-Jumping Mechanism, when the 3G-DCO arrives at the end-point of one clock-period region, it can immediately jump to the point in the adjacent clock-period region which has the closest clock period to the current one. In this way, we can overcome the discontinuity problem faced by most previous DCO’s to create an almost continuous frequency tracking range similar to an analog DCO, and make the ADPLL suitable for operations with temperature variation. Besides, the proposed ADPLL can be designed by following the general cell-based design flow, so that, it can decrease the design cycle time in a new process. Using TSMC 0.18□m CMOS technology, the simulation result shows that the three-gear digitally controlled oscillator designed in this work can operate from 89 MHz to 1013 MHz with 2.54 ps of average resolution (at TT-corner), and the proposed ADPLL has the RMS and the peak-to-peak jitter of 2.2 ps and 17 ps at 1000 MHz, respectively.