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Standard-Cell Placement for Low Power MTCMOS Design
Thesis

Standard-Cell Placement for Low Power MTCMOS Design

Tzu-Teng Lin
Masters, 國立清華大學, 資訊工程學系
2004

Abstract

低功率 標準單元配置 MTCMOS placement
Reducing power dissipation is one of the most important issues in VLSI design today. Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. The cluster-based MTCMOS design is proposed to reduce the virtual ground overhead. The sleep transistor size can be reduce by clustering mutual exclusive discharge cells together to minimize the simultaneous switching current per cluster and to share one sleep transistor per cluster. From [3], the sleep transistor size can be further reduced by considering topology and functionality simultaneously. However, this cluster-based MTCMOS design do not consider the placement issue. Therefore, we propose two standard cell placement algorithms for MTCMOS design to minimize wirelength overhead and sleep transistor size. The first one is a functionality directed placement algorithm and the second one is a direct placement with iterative cell-moving algorithm. The experimental results show that the chip area is reduced about 14.38% and the total wirelength increased about 32.43% compared to the direct placement by performing the functionality directed placement algorithm, and the chip area is reduced about 9.18% and the total wirelength increased about 5.16% compared to the direct placement by performing the direct placement with iterative cell moving algorithm.

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