Abstract
Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. On the other hand, the delay models of threshold logic gates accompanied with their implementation development have also been proposed. However, there has not been a timing analysis algorithm for threshold logic circuits to the best of our knowledge. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the path sensitization criterion for criticality analysis in threshold logic circuits is also different. In this work, we propose a path sensitization criterion for threshold logic circuits, and develop a static timing analysis algorithm. The experimental results show the accuracy and efficiency of the proposed algorithm compared to the dynamic simulation approach for a set of MCNC and IWLS 2005 benchmarks.