Abstract
Undoubtedly interconnect problems in VLSI designs deserve more attention and can no longer be neglected. In order to catch up with trend of System-on-Chip, sub-90nm process technology is introduced for increasing transitor numbers on the chip, off current reduction or low power requirement but also bring some new problems. One of them is process variation. Process variation is an overall challenge below 100 nm, and not just for interconnects. Therefore, analysis with these interconnect variations is the basis of accurate estimation of interconnect performance. Only by well assessment on process variation and continuous reformation on process technology that could improve the chance of successful design. In this paper, we present a non-destructive inverse modeling copper interconnect process flow which not only provide fast analysis on test structure and provide electrical characterization extraction but also integrate statistical and corner modeling method for metal interconnect manufacturability analysis. Based on our model, we could use silicon data form foundry to diagnose current manufacturing capability and to help analysts making decision between successful fabrication or review problems during process. We also provide sensitivity test helping analysts locate critical factors or eliminate the uninterested factors. This analysis could give assistance for foundry manufacturability and look forward to advanced technology. Conclusions and analysis methods of CMOS process problem diagnosis using the data obtained from test chip are summarized.