Abstract
Abstract In order to meet the requirements of high resolution and alignment accuracy, the lithography equipments have been advanced from step-and-repeat system to step-and-scan system. As the tolerance of linewidths is becoming tight and slight, overlay errors must be controlled within the tolerance to maintain the yield. In particular, overlay errors can be compensated by modifying the corresponding equipment setup parameters. However, most of the existing studies focused on the step-and repeat system. Little research has been done to deal with overlay errors of the step-and-scan system. This study aimed to construct the overlay error model for step-and-scan system and design the sampling strategy to measure and thus compensate the overlay errors. Furthermore, the proposed model and sampling strategy are validated by empirical studies conducted in a fab. We compared the proposed sampling strategy with alternative sampling strategies including the existing sampling strategies based on the model adequacy of R-squares and the model effectiveness of residual errors. The results demonstrated the practical viability of the proposed approach. Keywords: overlay, modeling, sampling strategy step-and-scan, semiconductor manufacturing