Abstract
Three-dimensional or 2.5-dimensional integrated circuits using Through Silicon Via (TSV) can improve performance and power. However, thermal and thermal-induced mechanical problems in 3D or 2.5D stacking-die technologies are known to be more severe than those in 2D circuits. A high temperature environment during the fabrication process of TSVs leads to uncontrollable thermal expansion, which then causes a serious reliability problem, the thermal mechanical problem. This problem can result in deformation or mechanical damage to the dies. In the first work, unlike previous works applying expensive components not in the standard CMOS process, we first present to use an “off-the-shelf” component, micro bumps, to relax the thermal mechanical stress. In addition, an efficient algorithm to place micro bumps in appropriate positions is also proposed. In the second work, many researches have proposed efficient TSV placement algorithms to alleviate the hot spot problem and to reduce the wire length. However, in addition to the thermal and wire length issues, we show TSV placement can also affect die fracture. Hence, we propose a novel TSV placement approach simultaneously considering die fracture, thermal, and wire length constraints.